“In Adreno tradition, Adreno X1’s first level cache is a dedicated texture cache. Compute accesses bypass the L1 and go to the next level in the cache hierarchy. It’s quite different from current AMD, Nvidia, and Intel GPU architectures, which have a general purpose first level cache with significant capacity. On prior Adreno generations, the GPU-wide L2 cache would have to absorb all compute accesses. Adreno X1 takes some pressure off the L2 by adding 128 KB cluster caches.”
People have been tinkering with L1 cache conditionality since the L1i and L1d split in 1976 but the Qualcomm people are going hard on this and the jury seems out how it’s going to play.
The line between the L1 and the register file has been getting blurrier every year for over a decade and I increasingly have a heuristic around paying the most attention to L2 behavior until the profiles are in but I’m admittedly engaging in alchemy.
Can any serious chip people as opposed to an enthusiastic novice like myself weigh in on how the thinking is shaping up WRT this?
People have been tinkering with L1 cache conditionality since the L1i and L1d split in 1976 but the Qualcomm people are going hard on this and the jury seems out how it’s going to play.
The line between the L1 and the register file has been getting blurrier every year for over a decade and I increasingly have a heuristic around paying the most attention to L2 behavior until the profiles are in but I’m admittedly engaging in alchemy.
Can any serious chip people as opposed to an enthusiastic novice like myself weigh in on how the thinking is shaping up WRT this?