Comment by artemonster

Almost every couple of years (and once a decade for something "big") there is a new development in the area mostly driven either by clueless software guys that wandered outisde their turf into hardware territory, or some university chair that sits in the undefined limbo between hardware and software (usually doing something in the realm of CGRAs) that has to justify its existence by offering a PhD to some guy that will create a new RTL IR or another deadborn HLS. Developing hardware is a solved problem. Has been for decades. And no, writing a sentence in your white paper that says something like "existing HDLs operate on gates and cycles and its not an appropriate level of abstraction for us" is not enough of a justification. If you need a fancy pseudo-DSL to hold your hand to be able to describe simple datapaths and FSMs for you then you wouldnt be able to develop anything hardware related that is remotely useful. You cannot abstract away the essence of this engineering task. What we actually need is a tighter verification loops and better (and more accessible) verification methodology so that hardware development is less daunting in the first place, not another DSL-to-RTL translator (even if extensible, like in calyx case)