The default DDR5 ECC is not exposed to the outside, not reported to the OS.
You only caught errors on DDR5 because it's stability is very brittle. Market forces push it to the limit - everybody cares about the MT/s and runs XMP unlike previous generations.
You only caught errors on DDR5 because it's stability is very brittle. Market forces push it to the limit - everybody cares about the MT/s and runs XMP unlike previous generations.