I worked on the A510 (codenamed Klein) at Arm on the L1 memory system design. It was a fun core to work on, really pushing the bounds of what you can do with an in order core and made me realise the out of order/in order boundary is a lot more blurry than you might think. Plenty of out of order stuff happening in the memory system for instance.
Whilst there's plenty of reuse from the A55 the memory system was sufficiently different we built the load store unit from scratch. I got the honor of writing the RTL for the new one (normally you'd start with existing RTL and rework it). I wonder how many years those files will live on til they decide to start afresh?
It's a real shame the microarchitecture of these things isn't more open articles like this give you some info but not the full picture. I can see why they described it as a '5 entry load buffer' for instance but it's not really accurate to the true microarchitecture. There's also lots of fun details of the crazy things you have to do to hit your frequency target (often where you just ignore certain rare hazard or error conditions and detect them later and fix it up).
I'm not at Arm any more (I work on Open Silicon now though around embedded/IoT/Security applications not application class CPU cores). I do miss the days of working on the A510, CPU design is a lot of fun.
Whilst there's plenty of reuse from the A55 the memory system was sufficiently different we built the load store unit from scratch. I got the honor of writing the RTL for the new one (normally you'd start with existing RTL and rework it). I wonder how many years those files will live on til they decide to start afresh?
It's a real shame the microarchitecture of these things isn't more open articles like this give you some info but not the full picture. I can see why they described it as a '5 entry load buffer' for instance but it's not really accurate to the true microarchitecture. There's also lots of fun details of the crazy things you have to do to hit your frequency target (often where you just ignore certain rare hazard or error conditions and detect them later and fix it up).
I'm not at Arm any more (I work on Open Silicon now though around embedded/IoT/Security applications not application class CPU cores). I do miss the days of working on the A510, CPU design is a lot of fun.