Because Verilog is not C where typically a line of code turns into several machine code commands. And even if you write inefficient code, CPUs are so fast that you won't notice it. In Verilog a simple "+" or "*" can turn into thousands of gates. Without understanding this your designs will be inefficient and slow. Unlike CPU cycles, silicon and transistors are not free.
Also for a design to be fast you need to use pipelining and to slice your combinational logic into thin layers. Again, you won't be able to do it without understanding how your code translates to gates.
Also for a design to be fast you need to use pipelining and to slice your combinational logic into thin layers. Again, you won't be able to do it without understanding how your code translates to gates.