Sadly the article explains nothing. For example, it doesn't explain how the Verilog (or VHDL) code will be implemented at gate level, is it expensive or not (in terms of gate count), how long the critical path will be, can we pipeline it, how to implement several writing ports etc.
I think that one shouldn't write Verilog/VHDL code unless one clearly understands how it will be transformed into gates.
I think that one shouldn't write Verilog/VHDL code unless one clearly understands how it will be transformed into gates.