The industry's currently shipping chips based on the 3nm process. I understand that it's mostly a marketing term (i.e. non-standardized), but I assume the actual transistor channel is within that order of magnitude.
Knowing that a silicon atom is larger than 0.1 nm, how can we possibly keep Moore's Law on track? It feels like we're close to hitting fundamental limits.
Knowing that a silicon atom is larger than 0.1 nm, how can we possibly keep Moore's Law on track? It feels like we're close to hitting fundamental limits.
Any insights would be much appreciated. Thanks!