Really cool article and I definitely appreciated the section at the end that compared ternary to CMOS.
But in order to use ternary in a real processor, as suggested by the article, we would need a much more formal definition of the voltage levels of the gate.
But in order to use ternary in a real processor, as suggested by the article, we would need a much more formal definition of the voltage levels of the gate.
Something like this: https://www.egr.msu.edu/classes/ece410/mason/files/Ch7.pdf
Without that it’s not clear how one could do timing analysis or do dynamic gate resizing to deal with practical issues like fanout.
Also, without the more formal definition it’s not even clear, to me anyway, what figures like 22 are even measuring.