Some risc-v chips can execute in order and avoid having spectre-like problems. I work at a IaaS where customers deploy through our hosted cicd and we are very interested in risc-v solving our multi-tenancy concerns.
GCC and clang already have enough support for risc-v that we have no concerns for support being there. If GCC and clang have what's necessary, everything else is fine.
The moment we see close to a juncture where we can put an order in for risc-v with very many cores, our investors are going to dump a massive round of funding.
Whether risc-v is popular or not doesn't matter. Our multi-tenant services won't have fundamental security isolation problems, everyone serving on x86_64 and ARM will. Looks like risc-v will dominate where things actually matter, unless some new iteration of OpenPOWER comes out.
GCC and clang already have enough support for risc-v that we have no concerns for support being there. If GCC and clang have what's necessary, everything else is fine.
The moment we see close to a juncture where we can put an order in for risc-v with very many cores, our investors are going to dump a massive round of funding.
Whether risc-v is popular or not doesn't matter. Our multi-tenant services won't have fundamental security isolation problems, everyone serving on x86_64 and ARM will. Looks like risc-v will dominate where things actually matter, unless some new iteration of OpenPOWER comes out.