"RISC" architectures are doing something effectively identical to uop fusion though. The real myth is the idea of a CISC/RISC dichotomy in the first place when frankly that notion only ever applied to the ISA specifications and not (except for the very earliest cores) CPU designs.
In point of fact beyond the instruction decode stage all modern cores look more or less identical.
In point of fact beyond the instruction decode stage all modern cores look more or less identical.