That's really interesting. Skimmed the paper really quickly, definitely need to do a deeper dive into the paper.
From the Abstract:
Despite Tiny Classifiers being constrained to a few hundred logic
gates, we observe no statistically significant difference in prediction performance in comparison to the best-performing ML
baseline. When synthesised as a Silicon chip, Tiny Classifiers
use 8-56x less area and 4-22x less power. When implemented
as an ultra-low cost chip on a flexible substrate (i.e., FlexIC),
they occupy 10-75x less area and consume 13-75x less power
compared to the most hardware-efficient ML baseline. On an
FPGA, Tiny Classifiers consume 3-11x fewer resources.
Seems like this would be a pretty significant result if true.
From the Abstract:
Despite Tiny Classifiers being constrained to a few hundred logic gates, we observe no statistically significant difference in prediction performance in comparison to the best-performing ML baseline. When synthesised as a Silicon chip, Tiny Classifiers use 8-56x less area and 4-22x less power. When implemented as an ultra-low cost chip on a flexible substrate (i.e., FlexIC), they occupy 10-75x less area and consume 13-75x less power compared to the most hardware-efficient ML baseline. On an FPGA, Tiny Classifiers consume 3-11x fewer resources.
Seems like this would be a pretty significant result if true.