Yes but RISC-V is very risc-y by the criteria Mashey proposes here. The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes. That's still very low compared to historical CISC. And I think the atomic instructions do RMW to memory, but they carefully avoid complicated address modes; they even dispense with register+immediate offset.
(The E variety of RISC-V is also a bit strange in having only 16 integer registers, but the rationale for that was supporting smaller chips and easier extensibility; it's still very clearly a load-store architecture where compute happens within registers. Arguably, compilers have also gotten better at staying within fewer registers and not spilling to memory. So "number of registers" as a criteria might have shifted a little bit.)
(The E variety of RISC-V is also a bit strange in having only 16 integer registers, but the rationale for that was supporting smaller chips and easier extensibility; it's still very clearly a load-store architecture where compute happens within registers. Arguably, compilers have also gotten better at staying within fewer registers and not spilling to memory. So "number of registers" as a criteria might have shifted a little bit.)