Should be "32-ish architectural registers". Real processors have a lot more registers but they are not directly visible. This is the whole reason why x86-64 is usable despite having only 16 architectural integer registers (or actually a little less than that).
The article doesn't get RISC-V instruction encoding right. It mentions compressed instructions, but instructions can also be longer than 32 bits. The important thing about RISC-V is that the instruction stream can easily be divided at instruction boundaries (unlike, say, x86 which is horrific to decode). This gives you most of the benefits of fixed size instructions and the benefits of extensibility when you need it.
The article doesn't get RISC-V instruction encoding right. It mentions compressed instructions, but instructions can also be longer than 32 bits. The important thing about RISC-V is that the instruction stream can easily be divided at instruction boundaries (unlike, say, x86 which is horrific to decode). This gives you most of the benefits of fixed size instructions and the benefits of extensibility when you need it.