Comment Comment by dhdc Related: https://insights.sigasi.com/opinion/jan/verilogs-major-flaw/This is why if you want complete determinism, use VHDL. Unlike verilog, VHDL was developped specifically for describing hardware behavior. parent dhdc 4 years ago
This is why if you want complete determinism, use VHDL. Unlike verilog, VHDL was developped specifically for describing hardware behavior.