Logged in just to upvote this and largely agree with you. Verilog/VHDL are stuck at the 1980s coding paradigm level, as if the industry grabbed the first working solution for automated hardware developement and has clung on to it.
> The problem is, it is hard, if not downright impossible, to get the industry to change.
Yes. I don't think it will until either, say, Intel does it by CEO fiat, like the Amazon memo, or a startup from outside somehow dominates the industry by using a different technology.
(I have worked both sides of this, a chip design startup that was bought by Cadence, and a medium size fabless semi company)
> I've gotten so many bogus replies that just show that the engineer has no idea what higher order functional programming with advanced type system is on any level, and I don't blame them, but this makes discussions extremely tiring.
"A monad is just a monoid in the category of endofunctors, what's the problem?"
(I'm joking, but this is an us problem and not a them problem, you can't evangelize things to people that they don't understand, and you have to reach them where they are. Yes, this is very hard work)
However one thing that us software types may not appreciate is that all the weird imperative stuff in Verilog that isn't synthesizable probably gets used in more lines of code than the synthesizable subset - because testbenches are absolutely critical to shipping hardware.
The hardware industry can't benefit from rapid iteration because every iteration costs a mask set.
> The problem is, it is hard, if not downright impossible, to get the industry to change.
Yes. I don't think it will until either, say, Intel does it by CEO fiat, like the Amazon memo, or a startup from outside somehow dominates the industry by using a different technology.
(I have worked both sides of this, a chip design startup that was bought by Cadence, and a medium size fabless semi company)
> I've gotten so many bogus replies that just show that the engineer has no idea what higher order functional programming with advanced type system is on any level, and I don't blame them, but this makes discussions extremely tiring.
"A monad is just a monoid in the category of endofunctors, what's the problem?"
(I'm joking, but this is an us problem and not a them problem, you can't evangelize things to people that they don't understand, and you have to reach them where they are. Yes, this is very hard work)
However one thing that us software types may not appreciate is that all the weird imperative stuff in Verilog that isn't synthesizable probably gets used in more lines of code than the synthesizable subset - because testbenches are absolutely critical to shipping hardware.
The hardware industry can't benefit from rapid iteration because every iteration costs a mask set.