In practice it makes no difference, because digital logic designers haven't used schematic capture in a very long time. They most commonly write Verilog (or SystemVerilog, which is a superset), and it looks a lot like C:
logic [31:0] a, b, average;
assign average = (a >> 1) + (b >> 1) + (a & b & 32'd1);
logic [31:0] a, b, average; assign average = (a >> 1) + (b >> 1) + (a & b & 32'd1);