The speed of light story is a fun conjecture, but given the discrepancy (30cm vs 5.5mm), I don't think that's it. Light travels slower in wires but not
that much slower, and increased design clocks don't explain the discrepancy either.
I think it's more likely that this is an artifact of the interconnect design. For example, the interconnect may be designed as a tree, where the path from core 0 to the L2 only visits a branch but the path to core1/2 has to traverse the root of the tree. If each stage adds a clock cycle, there's your 4 clock cycles: one to go to the root, one back down to the other side, and then the whole thing in the other direction for the reply from L2 with the data.
If the interconnect had been a ring bus instead, you'd find that the latency from cores 0 and 2 is the same, but higher for core 1 - assuming no other endpoints in the ring, but that's obviously not the case, since I/O needs to be on the bus too. It's possible he got the core numbers wrong in the die shot, and core 0 is the bottom left core. Then if the ring goes clockwise L2 - core 0 - core 1 - core 2 - I/O on the top right - L2, that's how you end up with core 0 being closer to the L2 in terms of clock cycles than the others, and the observation would be consistent with this design too.
I think it's more likely that this is an artifact of the interconnect design. For example, the interconnect may be designed as a tree, where the path from core 0 to the L2 only visits a branch but the path to core1/2 has to traverse the root of the tree. If each stage adds a clock cycle, there's your 4 clock cycles: one to go to the root, one back down to the other side, and then the whole thing in the other direction for the reply from L2 with the data.
If the interconnect had been a ring bus instead, you'd find that the latency from cores 0 and 2 is the same, but higher for core 1 - assuming no other endpoints in the ring, but that's obviously not the case, since I/O needs to be on the bus too. It's possible he got the core numbers wrong in the die shot, and core 0 is the bottom left core. Then if the ring goes clockwise L2 - core 0 - core 1 - core 2 - I/O on the top right - L2, that's how you end up with core 0 being closer to the L2 in terms of clock cycles than the others, and the observation would be consistent with this design too.