Chisel and this project are different; chisel is a programming language to design hardware while this is a build tool for hardware design.
In software we have a nice compilation process that transforms code into machine code. However, to "compile" an ASIC you go from a hardware description language like verilog (which basically describes the design) and pass it through a complicated pipeline that composes a number of different tools. Right now, engineers use ad-hoc flows that use bash/TCL to glue together all the parts --- the project posted above is an attempt to cleanly specify + control the "compilation" process.
In software we have a nice compilation process that transforms code into machine code. However, to "compile" an ASIC you go from a hardware description language like verilog (which basically describes the design) and pass it through a complicated pipeline that composes a number of different tools. Right now, engineers use ad-hoc flows that use bash/TCL to glue together all the parts --- the project posted above is an attempt to cleanly specify + control the "compilation" process.