as much as it pains to say me, but IMO its a wasted effort. we don't need new design languages. VHDL/Verilog "pain points" as RTL are tiny and don't require solving, we pretty much figured out design. Verification, on the other hand, is still an evolving (now stagnating) mess that needs inputs.
The biggest offender on that project list is FIRRTL. Cleary outgrew as someone's university work of "hey, lets do IR, but for RTL" without knowing anything of the industry, tools, etc. At best you can do the same with one reduced canonical simplified verilog source-to-source translation. at worst it does not do the primary function of "being" IR for RTL, because it should've been a graph, not another language with simplified syntax.
The biggest offender on that project list is FIRRTL. Cleary outgrew as someone's university work of "hey, lets do IR, but for RTL" without knowing anything of the industry, tools, etc. At best you can do the same with one reduced canonical simplified verilog source-to-source translation. at worst it does not do the primary function of "being" IR for RTL, because it should've been a graph, not another language with simplified syntax.