Comment by artemonster

ha! I guess you haven't worked as a designer or verification engineer, designing chips then? let me tell you: you work with a commitee-designed c++ like abomination language with 300 non-composible keywords that make no freaking sense. all of that crap grew from legacy-upon-legacy of crutches as an attempt to fix the goddamn broken-by-design verilog. Ultimately, this craplanguage + library that is 90% non-debuggable macros, works only with ~3 vendor simulators (all 3 would do different stuff on big designs and you are locked almost forever). When you simulate you designs, most of external components would be either encrypted blackboxes or be calling "magic" functions (called system tasks) that are absultely opaque to you and do some global side-effects. All of this multiplied by the fact that every statement is executed in parallel in your huge design and evolves in time. Oh, did I mention how crappy the actual tools are? Think of 90's era with outdated and moronic UI/UX, some poorely integrated quasi-TCL interpreter for configuration & ability to crash that tool in <3 clicks. Ah, you will be paying 15kUSD/year per license, thank you very much. You will be needing lots of them (> 50).