Really nice tool to code FPGA, and hopefully by introducing more powerful tools will encourage and enable more people to utilize FPGA in their products and solutions design.
Just wondering if you are also planning to support FIRRTL in addition to Verilog? It is an intermediate representation for later versions of Chisel and previous discussions on HN [1].
In your Silice descriptions, you did mention about utilizing Lua, can you explain its relationship with Silice?
Just wondering if you are also planning to support FIRRTL in addition to Verilog? It is an intermediate representation for later versions of Chisel and previous discussions on HN [1].
In your Silice descriptions, you did mention about utilizing Lua, can you explain its relationship with Silice?
[1]https://news.ycombinator.com/item?id=21340009