The table in the article suggests to me that instead of this fictional "feature size", we could use the achievable transistor area as a more meaningful measure of process scale.
IBM achieved 50B transistors in 150mm^2, for a per-transistor area of 3000 nm^2.
TSMC's 5nm process (used by Apple's M1 chip) apparently achieves a transistor area of 5837 nm^2, while Intel's 10nm is lagging at roughly 10000 nm^2.
IBM achieved 50B transistors in 150mm^2, for a per-transistor area of 3000 nm^2.
TSMC's 5nm process (used by Apple's M1 chip) apparently achieves a transistor area of 5837 nm^2, while Intel's 10nm is lagging at roughly 10000 nm^2.