The company I'm working for is only using HLS since quite some time, no directly written Verilog etc. anymore. I myself am a software developer in this company.
I know it's working perfectly fine for us and even the strongest advocate of using Verilog directly was converted by now to only using HLS.
I got it explained like this:
HLS has it's own class of problems and you definitively need some time to get used to how you need to write code that is actually synthesized in a way you intended it to be. However, once you got used to it, development using HLS is way faster than writing Verilog directly and our FPGA guys basically said that we would not be where we are if it weren't for HLS because of this.
So it seems that it's actually working quite fine in practice but obviously not without it's own problems.
I know it's working perfectly fine for us and even the strongest advocate of using Verilog directly was converted by now to only using HLS.
I got it explained like this: HLS has it's own class of problems and you definitively need some time to get used to how you need to write code that is actually synthesized in a way you intended it to be. However, once you got used to it, development using HLS is way faster than writing Verilog directly and our FPGA guys basically said that we would not be where we are if it weren't for HLS because of this.
So it seems that it's actually working quite fine in practice but obviously not without it's own problems.