https://news.ycombinator.com/item?id=25257932My 10,000' view understanding:
- Small feature size. M1 is a 5nm process. Intel is struggling to catch up to TSMC's 7nm process
- more efficient transistors. 7nm uses finFet. M1 probably uses GAAFET, which means you can cram more active gate volume in less chip footprint. This means less heat and more speed
- layout. M1 is optimized for Apple's use case. General purpose chips do more things, so they need more real estate
- specialization. M1 offloads oodles of compute to hardware accelerators. No idea how their code interfaces with it, but I know lots of the demos involve easy-to-accellerate tasks like codecs and neural networks
- M1 has tons of cache, IIRC, something like 3x the typical amount
- some fancy stuff that allows them to really optimize the reorder buffer, decoder, and branch prediction, which also leverages all that cache
My 10,000' view understanding:
- Small feature size. M1 is a 5nm process. Intel is struggling to catch up to TSMC's 7nm process
- more efficient transistors. 7nm uses finFet. M1 probably uses GAAFET, which means you can cram more active gate volume in less chip footprint. This means less heat and more speed
- layout. M1 is optimized for Apple's use case. General purpose chips do more things, so they need more real estate
- specialization. M1 offloads oodles of compute to hardware accelerators. No idea how their code interfaces with it, but I know lots of the demos involve easy-to-accellerate tasks like codecs and neural networks
- M1 has tons of cache, IIRC, something like 3x the typical amount
- some fancy stuff that allows them to really optimize the reorder buffer, decoder, and branch prediction, which also leverages all that cache