If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface:
https://github.com/efabless/caravel/blob/master/verilog/rtl/...
The openlane tool converts your verilog all the way down to final ASIC design...
You'd need to license everything Apache 2.0 though. And it would have to be done soon, the deadline is Nov 30th.
If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/...
The openlane tool converts your verilog all the way down to final ASIC design...
You'd need to license everything Apache 2.0 though. And it would have to be done soon, the deadline is Nov 30th.