The board seems much less interesting than this feature it delivers. "CHERI" sounds really cool. At first I thought it was a rehash of pointer auth/hw sanitizer ARM features that already exist. But no [1]:
> A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V.
Something that can work across architectures will see much faster adoption, I'm happy to see it.
> A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V.
Something that can work across architectures will see much faster adoption, I'm happy to see it.
[1] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf