By EQ values I assume you're referring to the calibration results. These are typically called Delay Registers.
Yes, before signing-off on a system, we carefully look at the calibration result and see if there is enough margin.
Now what do I mean by margin? - The delay registers hold some sort of an integral value and there is a certain range to it, for example 0 to 7. You typically don't want the result to be at the ends. Because you want to give periodic calibration (which could run due to big temperature swings) a little margin.
If the calibration result does end up at the ends of the range, we have to play around with other DRAM timing parameters, which are managed by the DDR controller.
Yes, before signing-off on a system, we carefully look at the calibration result and see if there is enough margin.
Now what do I mean by margin? - The delay registers hold some sort of an integral value and there is a certain range to it, for example 0 to 7. You typically don't want the result to be at the ends. Because you want to give periodic calibration (which could run due to big temperature swings) a little margin.
If the calibration result does end up at the ends of the range, we have to play around with other DRAM timing parameters, which are managed by the DDR controller.