Been around for a while (at least the proprietary stuff). Certain things that are mere "style" and don't affect runtime for traditional C++ do have large effects on the generated code though. Intermediate variables for example will affect how many pipeline stages it generates (at least with Vivado).
Its a cool tool, but right now it's more of a productivity aide for people who already understand Verilog/VHDL rather than an enabler for software engineers.
Its a cool tool, but right now it's more of a productivity aide for people who already understand Verilog/VHDL rather than an enabler for software engineers.