A few random thoughts:
* Air presumably doesn't mean atmospheric air here, otherwise you're getting a random mix of gases and water vapour inside your nanoscale wizardry - so will these be nitrogen-filled, like binoculars etc?
* What does this mean for cooling, especially in the high-density 3D architectures mentioned? Can you use air flow through the chip to cool it?
* "tungsten, gold, and platinum were evaluated as metals of choice" - compare their resistivities of 5.60e-8, 2.44e-8, and 1.06e-7 ohm-metres respectively to silicon's of 6.4e+2 [1] (i thought tungsten was much higher than that, TIL). Does this mean that chips would have less resistive heating? Is resistive heating a significant part of the TDP of a modern chip?
* "replacing silicon with metal means these ACT devices can be fabricated on any dielectric surface, provided the underlying substrate allows effective modulation of emission current from source to drain with a bottom-gate field" - is there is also a lattice-spacing constraint, where the substrate's spacing has to work with that of the conductor, as i believe there is with silicon chips?
* Is this basically the return of the thermionic valve after fifty years in the wilderness?
[1] https://en.wikipedia.org/wiki/Electrical_resistivity_and_con...
* Air presumably doesn't mean atmospheric air here, otherwise you're getting a random mix of gases and water vapour inside your nanoscale wizardry - so will these be nitrogen-filled, like binoculars etc?
* What does this mean for cooling, especially in the high-density 3D architectures mentioned? Can you use air flow through the chip to cool it?
* "tungsten, gold, and platinum were evaluated as metals of choice" - compare their resistivities of 5.60e-8, 2.44e-8, and 1.06e-7 ohm-metres respectively to silicon's of 6.4e+2 [1] (i thought tungsten was much higher than that, TIL). Does this mean that chips would have less resistive heating? Is resistive heating a significant part of the TDP of a modern chip?
* "replacing silicon with metal means these ACT devices can be fabricated on any dielectric surface, provided the underlying substrate allows effective modulation of emission current from source to drain with a bottom-gate field" - is there is also a lattice-spacing constraint, where the substrate's spacing has to work with that of the conductor, as i believe there is with silicon chips?
* Is this basically the return of the thermionic valve after fifty years in the wilderness?
[1] https://en.wikipedia.org/wiki/Electrical_resistivity_and_con...