Due to all that legacy the instruction decoder has a lot less opportunity for optimizations.
There may be a physical limit to the size of transistors but the limit of computing performance is not ‘what Intel is doing’. There’s more to performance than instructions per second or clock frequencies. In fact these don’t lead to the same performance at all as ARM is RISC and x64 is CISC.
There may be a physical limit to the size of transistors but the limit of computing performance is not ‘what Intel is doing’. There’s more to performance than instructions per second or clock frequencies. In fact these don’t lead to the same performance at all as ARM is RISC and x64 is CISC.