Chisel has better type safety than Verilog yet it's much less verbose than VHDL. Verilog is the industrial language of choice at most ASIC shops, and there are things like VerilogAMS (mixed signal) and SystemVerilog (validation) that will keep it entrenched for a long time. If you didn't have to care about ecosystem, my amateur opinion is that Chisel > VHDL > SystemVerilog > Verilog.
I wasn't sure how seriously to take Chisel until I saw the RISC-V BOOM definition https://github.com/ucb-bar/riscv-boom. It's clean, succinct, and I think Chisel is quite viable.
It's also a testament to the symbolic nature of Scala. It holds together pretty well in JVM, ScalaJS, Chisel, and scala-native. Scala as a language is remarkably simple at the core, which Odersky does a good job of showing in his book, even though there are a lot of library features on top that make it complex and a more difficult language in general use. In this way of having a cute core, it is very unlike C++.
I wasn't sure how seriously to take Chisel until I saw the RISC-V BOOM definition https://github.com/ucb-bar/riscv-boom. It's clean, succinct, and I think Chisel is quite viable.
It's also a testament to the symbolic nature of Scala. It holds together pretty well in JVM, ScalaJS, Chisel, and scala-native. Scala as a language is remarkably simple at the core, which Odersky does a good job of showing in his book, even though there are a lot of library features on top that make it complex and a more difficult language in general use. In this way of having a cute core, it is very unlike C++.