This is very interesting but does not appear to be helpful for the development of my TTA processor design. It appears that this project aims for more parallelism similar to VLIW than my simple MOVE architecture targets.
I would very much appreciate feedback and suggestions regarding my preliminary specifications which will be changing in the near future (before year's end) to include MUL, DIV, and floating point support. I really want to have a firm specification before proceeding with the VHDL implementation.
I would very much appreciate feedback and suggestions regarding my preliminary specifications which will be changing in the near future (before year's end) to include MUL, DIV, and floating point support. I really want to have a firm specification before proceeding with the VHDL implementation.
You can view what I have done at https://github.com/BillBohan/NISC .