An aligned word won't span a cache line. So any aligned 64-bit or 128-bit word is always wholly within a single cache line.
But two 32-bit words can span a cache line if the first isn't 64-bit aligned. So what you're doing relies on hardware supporting atomic operations not only on unaligned words, but on words spanning cache lines. Are you really sure ARM and POWER support that?
But two 32-bit words can span a cache line if the first isn't 64-bit aligned. So what you're doing relies on hardware supporting atomic operations not only on unaligned words, but on words spanning cache lines. Are you really sure ARM and POWER support that?