VHDL and Verilog are virtually no different from eachother. It's basically equivalent to ARM assembly vs MIPS assembly -- they are both machine-level assembly languages.
If you want something more interesting, see High Level Synthesis (aka C to RTL, SystemC, etc) [1]. But this is still very beta (and has been for over a decade), so it's almost unused in the industry on designs.
The majority of hardware design time is now dominated in the hardware verification space, aka SystemVerilog.
If you want something more interesting, see High Level Synthesis (aka C to RTL, SystemC, etc) [1]. But this is still very beta (and has been for over a decade), so it's almost unused in the industry on designs.
The majority of hardware design time is now dominated in the hardware verification space, aka SystemVerilog.
[1] https://en.wikipedia.org/wiki/High-level_synthesis