This being HN, I'm hoping someone more competent than me in the area of CPU architectures can comment, but as a scientific programmer some of the details lead me to adopt a very cautious attitude for now, especially given the 95W TDP. Given the architecture, producing a performance-competitive 8C/16T chip at 68% of Intel's TDP (95W vs 140W) seems very dubious.
Most of the things they're touting in the slides amount to little more than finally catching up to Intel (SMT, branch prediction (minus the neural network thing), cache bandwidth, etc.). Also, some of the areas where they seem to exceed current Intel architectures may turn out to be a mixed blessing. For instance, I'm not sure if doubling L2 caches (512kb/core vs 256kb in Intel CPUs) is a great idea given bandwidth limitations and associativity effects. We also don't know the amount of vector registers these CPUs will have, which will greatly influence the performance of optimal CPU-bound code.
Can anyone with more experience comment on the low level details they've released, particularly the issues per cycle and cache architecture figures?
Most of the things they're touting in the slides amount to little more than finally catching up to Intel (SMT, branch prediction (minus the neural network thing), cache bandwidth, etc.). Also, some of the areas where they seem to exceed current Intel architectures may turn out to be a mixed blessing. For instance, I'm not sure if doubling L2 caches (512kb/core vs 256kb in Intel CPUs) is a great idea given bandwidth limitations and associativity effects. We also don't know the amount of vector registers these CPUs will have, which will greatly influence the performance of optimal CPU-bound code.
Can anyone with more experience comment on the low level details they've released, particularly the issues per cycle and cache architecture figures?