The Epiphany-V was designed using a completely automated flow to translate Verilog RTL source code to a
tapeout ready GDS, demonstrating the feasibility of a 16nm “silicon compiler”. The amount of open source
code in the chip implementation flow should be close to 100% but we were forbidden by our EDA vendor
to release the code. All non-proprietary RTL code was developed and released continuously throughout the
project as part of the “OH!” open source hardware library.[20] The Epiphany-V likely represents the first
example of a commercial project using a transparent development model pre-tapeout.
The Epiphany-V was designed using a completely automated flow to translate Verilog RTL source code to a tapeout ready GDS, demonstrating the feasibility of a 16nm “silicon compiler”. The amount of open source code in the chip implementation flow should be close to 100% but we were forbidden by our EDA vendor to release the code. All non-proprietary RTL code was developed and released continuously throughout the project as part of the “OH!” open source hardware library.[20] The Epiphany-V likely represents the first example of a commercial project using a transparent development model pre-tapeout.