Alright, this is just one of those topics that it's hard to get prior Google results out of that were good. All papers have same terms in them. (sighs) I did find something to illustrate the problem, though.
http://alacron.com/clientuploads/PDFs/Applications/FocusedIo...
This describes micromilling semiconductors with focused, ion beams. Now, you said not FIB lithography. I can't be sure this is what you're talking about but it's pretty direct. Regardless, all the schemes work similarly in that you work on one part at a time across a chip or wafer. In this one, you can see the precision work is so time consuming that it can take 8 hours for first, metal layer in a chip with quite a few of them. Another part says days. Whereas, even old uses of masks with steppers were cranking out three wafers per minute. See the difference? That's why the direct technologies, even multiple beams, are usually used for just the photomask (most fabs) or for prototypes (eASIC).
I did find that fab I was telling you about that used tech like this:
http://www.nytimes.com/1988/08/01/business/chip-maker-withou...
It was doing it on nodes that are ancient by today's standards. Yet, you could do quite a bit with them. The lead time was only four weeks for quite a few chips at a reasonable price. Better capabilities can be had at less price today. I keep saying target 0.35 micron initially as it's inexpensive with many fabs available and last cheap one with visual inspection possible. Plus, OSS flows should work on it. Use one beam fab for cheap ones plus one for at least 90nm with 65nm or 45nm high-end.
Far as recent companies, the eASIC process is maskless at 90nm, 45nm, and 28nm for prototyping. THey mainly do structured ASIC's. Here's an example of the prototyping cost:
http://www.easic.com/easic-introduces-45nm-asic-value-shuttl...
http://alacron.com/clientuploads/PDFs/Applications/FocusedIo...
This describes micromilling semiconductors with focused, ion beams. Now, you said not FIB lithography. I can't be sure this is what you're talking about but it's pretty direct. Regardless, all the schemes work similarly in that you work on one part at a time across a chip or wafer. In this one, you can see the precision work is so time consuming that it can take 8 hours for first, metal layer in a chip with quite a few of them. Another part says days. Whereas, even old uses of masks with steppers were cranking out three wafers per minute. See the difference? That's why the direct technologies, even multiple beams, are usually used for just the photomask (most fabs) or for prototypes (eASIC).
I did find that fab I was telling you about that used tech like this:
http://www.nytimes.com/1988/08/01/business/chip-maker-withou...
It was doing it on nodes that are ancient by today's standards. Yet, you could do quite a bit with them. The lead time was only four weeks for quite a few chips at a reasonable price. Better capabilities can be had at less price today. I keep saying target 0.35 micron initially as it's inexpensive with many fabs available and last cheap one with visual inspection possible. Plus, OSS flows should work on it. Use one beam fab for cheap ones plus one for at least 90nm with 65nm or 45nm high-end.
Far as recent companies, the eASIC process is maskless at 90nm, 45nm, and 28nm for prototyping. THey mainly do structured ASIC's. Here's an example of the prototyping cost:
http://www.easic.com/easic-introduces-45nm-asic-value-shuttl...