Comment by yuubi

MIPS, the Microprocessor without Interlocked Pipeline Stages, doesn't make sure the result of one instruction is available before executing an instruction "later" in the stream that refers to that result. Something like (pseudo-asm with C-notation comments)

     ld r1, @r2   ; r1 = *r2
     add r3,r1,r4 ; r3 = r1+r4

wouldn't set r3=*r2+r4 because the memory access hasn't finished by the time the add runs.