I've been trying to encourage America and Europe to do this with EDA tooling and I.P.. To no avail. Idea is that the whole flow gets good tools, cell libraries, and info on processes that nearly guarantees first pass. Then, a whole platform of I.P., esp I/O or accelerators, are built on several nodes for easy integration and shrinking of third party designs. Multi-project wafers are streamlined for each of those nodes. You get all that free (except MPW's) if you use the host's tooling and fabs with local fabless getting a tax deduction potentially.
Such a setup could make for a HW equivalent of what's happening in embedded with Arduino's etc. A slower pace due to costs but still better than now. Plus, an existing SOC platform at 45nm and 28nm would be great for cloud datacenters that are investigating custom hardware for accelerators and cost reduction. We'd see shit cranking out constantly for that market.
So, it's now up to China. They can have that blueprint of mine for free. I'd also consult on the specifics since nobody here is doing it outside a few academics and smaller firms. Gotta create the end result somehow.
Note to Chinese involved reading: Also, do a FPGA at 28nm and 28SLP with open bitstream and free tooling at low cost. Make ASIC conversions easy with paid, Chinese I.P. as an upsell. Probably sell the heck out of those FPGA's and academics will do most of R&D on their EDA just for fun. Acquire Achronix while you're at it to do the same with their asynchronous stuff. Acquire eASIC and/or Triad for RAD hardware at a discount for Chinese firms. Same advice I give here should help there.
Such a setup could make for a HW equivalent of what's happening in embedded with Arduino's etc. A slower pace due to costs but still better than now. Plus, an existing SOC platform at 45nm and 28nm would be great for cloud datacenters that are investigating custom hardware for accelerators and cost reduction. We'd see shit cranking out constantly for that market.
So, it's now up to China. They can have that blueprint of mine for free. I'd also consult on the specifics since nobody here is doing it outside a few academics and smaller firms. Gotta create the end result somehow.
Note to Chinese involved reading: Also, do a FPGA at 28nm and 28SLP with open bitstream and free tooling at low cost. Make ASIC conversions easy with paid, Chinese I.P. as an upsell. Probably sell the heck out of those FPGA's and academics will do most of R&D on their EDA just for fun. Acquire Achronix while you're at it to do the same with their asynchronous stuff. Acquire eASIC and/or Triad for RAD hardware at a discount for Chinese firms. Same advice I give here should help there.