> As you can see here the SIMD (NEON) extension adds 16 – 128 bit registers (q0-q15) onto the floating point registers. So if you reference Q0 it is the same as referencing D0-D1 or S0-S1-S2-S3.
Is this how SIMD is usually implemented in hardware? Have a set of circuitry that pushes one command to multiple registers?
Is this how SIMD is usually implemented in hardware? Have a set of circuitry that pushes one command to multiple registers?